Archive | September, 2012

An Approach to 20nm IC Design

10 Sep

Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.

Here’s a quick overview of the challenges, approaches to overcome the challenges and then the impact.

Challenges Approach Impact
Lithography Double Patterning Technology (DPT) More masks, mask costs of $5M to $8M, new DPT-aware EDA tools, new DPT-aware cells and IP,
Variability Early analysis of Layout Dependent Effects (LDE) New EDA tool flows, new design rules
Design Complexity Re-use IP, more verification, mixed-signal design, 3D, TSV Longer schedules, AMS tools required, SoC design costs $120M – $500M

Benefits of 20nm

With these challenges at 20nm versus 28nm the goal is to exploit the technology with products that have:

  • 30-50% performance improvement
  • 30% dynamic power savings
  • 50% area reduction
  • Up to 12 billion transistors


A picture is worth 1,000 words so here’s the story of why we need to use two masks for a single layer in order to resolve the patterns in silicon:

On the left is what happens when using a single mask and trying to produce small patterns at 20nm dimensions, while on the right is the much improved manufacturing result when using two masks for the same layer. With DPT each complex layout pattern is separated with enough spacing to allow the 192nm lithography equipment to adequately resolve without interference from neighboring patterns. Only the lowest mask layers in 20nm require this special treatment, but it will cost you more in mask expenses.

All of the EDA tools that create IC layout must be updated to take into account how to create DPT patterns. Once you’ve made something like a standard cell, then you need to ensure that when that cell is placed, flipped or mirrored, that it still is DPT compliant:

In the above layout the layer has been colorized into red and green, denoting the two different masks required for DPT. With new automation the IC designer doesn’t have to think about how to make their IC layout DPT compliant, because a manual coloring would be too tedious and error prone.

Connecting the standard cells together is done by a Place and Route tool, so it needs to be updated to become DPT aware as well.

Extraction tools read these layouts to create a netlist for either circuit simulation or static timing analysis, and with DPT awareness it will take into account mask offsets that change the parasitic R, C and L values.

The DRC tools likewise have to take into account the hundreds of new rules at 20nm

The foundries want high yield and to ensure that yield they characterize the silicon and produce layout rules that need to be followed by layout and circuit designers. At 20nm you can expect about 5,000 design rule checks (DRC). What’s new at 20nm compared to 28nm are about 40 rules for DPT and 400 rules for things like layout directional orientation, transistor proximity and inter-digitation patterns.

Variations in the actual layout across the die need to be taken into account and simulated prior to tapeout, this means more circuit simulation, stating timing analysis, and statistical timing analysis. With 20nm there can be more coupling between nets and that will in turn impact sensitive analog circuits or memory cells.

One Layout Dependent Effect is how the Voltage Threshold (Vt) of an MOS device changes based on the proximity to the well layer:

In this diagram the MOS transistor is show at the top, and as the transistor is placed closer to the well the value of Vt goes up. This variation in Vt will impact the gain and speed of the transistor, so on the right is a chart showing the gain of the transistor and the design rule manual (DRM) recommendation for a safe spacing, active to NWell.

Even the placement of standard cells will trigger layout dependent effects that impact timing:

The good news is that all of these effects can be analyzed early in the design process through tools that have been made LDE aware:

Design Complexity

Sequential IC design flows have given way to concurrent design flows where the goal is to Prevent, Analyze and Optimize. Specific examples of this approach include:

  • Constraint-driven design
  • LDE aware placement
  • Color-aware place and route
  • In-design verification

Power, Performance and Area (PPA) goals define each SoC spec, and to meet specs you need to support complex clocking, multiple power domains, and automated low power techniques. One such approach is called clock concurrent design where concurrent optimization is used:


Cadence has been collaborating with foundries (IBM, GLOBALFOUNDRIES, Samsung, TSMC) at the earliest development stages of 20nm and below nodes to update the IC tool flows to ensure an automated approach to SoC design that follows a methodology of Prevent, Analyze and Optimize.


16 free fall Stanford classes that will help you build your business

10 Sep

 16 free fall Stanford classes that will help you build your business

Anyone building a business, listen up: Stanford is offering 16 free, online courses for anyone looking to pick up a few extra skills. The courses include some technology and entrepreneurship-based subjects that could help you get that edge you need.

Stanford University is the institution for entrepreneurship. In its history, the university spit out notable alumni such as Vint Cerf, now vice president and chief Internet evangelist at Google, Google co-founders Sergey Brin and Larry Page, William Hewlett and David Packard of HP, and a number of recognizable technology enthusiasts.

It encourages students to start businesses, and offers courses to that end. Now it’s offering 16 free courses with focuses in business, entrepreneurship, technology, and science. But you don’t have to be a full-time student at Stanford to take advantage. The university says, “the courses are open to anyone with a computer, anywhere.”

For nine of these courses, Stanford is using Coursera, which partners with universities across the country to organize and launch free courses. It thus far has 16 participating universities, in addition to $16 million in its first round of funding. “Writing in the Sciences” and “Human-Computer Interaction” are two of Stanford’s courses being hosted by the startup.

There are a number of courses that could come in handy for someone trying to start a business in the Valley. Here’s a list of what’s coming up this fall:

  1. Machine Learning with Professor Andrew Ng, starting August 20
  2. Cryptography with Professor Dan Boneh, starting August 27
  3. Introduction to Mathematical Thinking with Professor Keith Devlin, starting September 17
  4. Probabilistic Graphical Models with Professor Daphne Koller, starting September 24
  5. Human-Computer Interaction with Professor Scott Klemmer, starting September 24
  6. Introduction to Logic with Professor Michael Genesereth, starting September 24
  7. Organizational Analysis with Professor Dan McFarland, starting September 24
  8. Writing in the Sciences with Professor Kristin Sainani, starting September 24
  9. Algorithms: Design and Analysis, Part 2 with Professor Tim Roughgarden starting in October
  10. Technology Entrepreneurship with Professor Chuck Eesley, starting in the fall
  11. A Crash Course on Creativity with Professor Tina Seelig, starting in the fall
  12. Designing a New Learning Environment with Professor Paul Kim, starting in the fall
  13. Finance with Professor Kay Giesecke, starting in the fall
  14. Startup Boards: Advanced Entrepreneurship with Professor Clint Korver, starting in the fall
  15. Solar Cells, Fuel Cells and Batteries with Professor Bruce Clemens, starting October 8
  16. An Introduction to Computer Networks with Professors Nick McKeown and Philip Levis, starting October 8

Stanford image via brianc/Flickr